This application claims priority from Korean Patent Application Nos. 10-2005-0058437 filed on Jun. 30, 2005 and 10-2005-0058444 filed on Jun. 30, 2005, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
1. Field of the Invention
The present invention relates to a thin film transistor (TFT) plate and a method of fabricating the same, and more particularly, to a TFT plate having improved processing efficiency without degradation in performance and a method of fabricating the TFT plate.
2. Description of the Related Art
Recently, in liquid crystal displays (LCDs) used as display devices for notebook computers or other portable devices, driving methods thereof are shifting from a simple matrix type to an active matrix type. In particular, a thin-film transistor (TFT) active matrix driving method has become the mainstream technology for driving the LCDs.
A TFT generally includes a gate electrode as a part of a gate line, a semiconductor layer forming a channel, a source electrode as a part of a data line, and a drain electrode facing the source electrode on the semiconductor layer. The TFT is generally used as a switching element for transmitting or blocking a data signal received through the data line by a gate signal transferred through the gate line.
The semiconductor layer is made of amorphous silicon or polycrystalline silicon. A thin-film transistor is categorized into a bottom-gate type and a top-gate type according to its position relative to a gate electrode. A polycrystalline silicon TFT is usually of a top gate type in which a gate electrode is disposed above an active layer.
A driving speed of the polycrystalline silicon TFT is much faster than that of the amorphous silicon TFT. Thus, the polycrystalline silicon TFT is advantageously able to form a driving circuit in cooperation with TFTs of pixel. However, there is a punch-through problem with the polycrystalline silicon TFT. To overcome this problem, it is preferable to form a lightly doped region between a channel region and the source/drain regions of the semiconductor layer.
According to a conventional method for forming a lightly doped region, a gate electrode is comprised of two conductive layers on a semiconductor layer, one of which is used as a mask for defining a lightly doped region and the other of which is used as a mask for defining a source region and a drain region after the formation of the lightly doped region. However, forming two conductive layers in different patterns through one-time photolithography makes the manufacturing process complicated and difficult to define the width of the lightly doped region. As a result, the entire process time increases, causing a decrease in fabrication yield.